1. Field of the Invention
The present invention relates generally to analog to digital converters (ADC), and more specifically to a high-speed high-resolution ADC that uses successive approximation techniques.
2. Related Art
Analog to digital converters (ADCs) are used to generate a sequence of digital codes representing the respective signal levels of an analog signal as is well known in the relevant art. In general, an ADC receives a reference voltage also as input, with the voltage indicating the maximum input voltage level.
Assuming the ADC is to generate an N-bit digital code on a linear scale, a digital code ideally equals (Vin * 2N/Vref), wherein Vref, Vin, * and / respectively represent the reference voltage, voltage level of a sample of the input signal, multiplication operator and division operator. In addition, a voltage level corresponding to one least significant bit (LSB) equals (Vref/2N).
ADCs often employ successive approximation principle (SAP) for such a conversion. In a typical SAP based implementation, each bit of a digital code (with the digital code representing a sample of the analog signal) is determined in a single iteration, starting from the most significant bit. To determine the most significant bit, the most significant bit is set to a specific logical value (e.g., 1) and the following bits to the other logical value (0), and the resulting number is converted to an intermediate analog signal (generally using a digital to analog converter (DAC), contained in the ADC).
Assuming the specific logical value equals 1, the value of the most significant bit of the digital code is determined to equal 0 if the sample of the analog signal has less voltage than the intermediate analog signal, or else to 1. The next significant bit may be set to 1 (while setting the most significant bit to the determined value) and the following bits to 0, and the resulting number is used to generate a new intermediate analog signal.
The new intermediate analog signal is compared with the sample of the analog signal to determine the corresponding (next significant) bit of the digital code. The approach is continued until all the bits of the digital code are determined. Other digital codes representing an analog signal may be generated at a desired sampling interval.
SAP technique is often used for reasons such as simplicity of implementation, accuracy of output, etc. However, one problem with SAP technique is that the throughput performance of the technique is low (i.e., may take a long duration to complete a conversion) due to the iterative nature of resolving the value of each bit position.
The problem is compounded in case ADCs are to be implemented with a high resolution (number of bits in each converted digital code) since the number of iterations according to SAP may equal the number of bits in each digital code. It is therefore desirable to provide ADCs using SAP, but with high throughput performance.